Pattern formed on the ground layer of a multilayer printed circuit board



FIG. 1 shows a front view of the design according to a first embodiment of the present invention.

FIG. 2 shows a back view of the design according to a first embodiment of the present invention.

FIG. 3 shows a top plan view of the design according to a first embodiment of the present invention.

FIG. 4 shows a bottom plan view of the design according to a first embodiment of the present invention.

FIG. 5 shows a left side view of the design according to a first embodiment of the present invention.

FIG. 6 shows a right side view of the design according to a first embodiment of the present invention.

FIG. 7 shows a partial view of FIG. 1 corresponding to the area indicated by the dashed box in FIG. 1.

FIG. 8 shows a detailed view of an enlarged portion of FIG. 7 indicated by the dashed box in FIG. 7.

FIG. 9 shows a sectional view along the line 9—9 indicated in FIG. 7.

FIG. 10 shows a front plan view of the design according to a second embodiment of the present invention. In this embodiment, the ground layer is transparent.

FIG. 11 shows a back view of the design according to a second embodiment of the present invention.

FIG. 12 shows a top plan view of the design according to a second embodiment of the present invention.

FIG. 13 shows a bottom plan view of the design according to a second embodiment of the present invention.

FIG. 14 shows a right side view of the design according to a second embodiment of the present invention.

FIG. 15 shows a left side view of the design according to a second embodiment of the present invention.

FIG. 16 shows a partial view of FIG. 11 corresponding to the area indicated by the dashed box in FIG. 11.

FIG. 17 shows a detailed view of an enlarged portion of FIG. 17 indicated by the dashed box in FIG. 17; and,

FIG. 18 shows a sectional view along the line 19—19 indicated in FIG. 17.

The broken lines represent unclaimed subject matter. 

The ornamental design for a pattern formed on the ground layer of a multilayer printed circuit board, as shown and described. 